The present invention relates to a charge-coupled device (CCD), and more particularly, to the structure of a linear CCD and a method of operating the same, in which the structure of the connecting part of a photodiode and a charge transfer part and the transfer method of a signal charge are improved to be suitable for a high speed linear CCD.
A CCD is an imaging device in which, with a pulse voltage applied to a gate electrode, a potential well is formed in the vicinity of the surface of a semiconductor to move charges that exist in the well.
As one example of conventional linear CCDs, a schematic layout is shown in FIG. 1. This conventional linear CCD comprises a photodiode-array 10, charge transfer parts (horizontal analog shift resistors) 13 and 14 located on both sides of the photodiode-array, shift gates 11 and 12 for transferring a charge generated from the photodiode 10 to the charge transfer parts 13 and 14, an output gate (OG) 15 for transmitting the charge transferred from charge transfer parts 13 and 14 to an output terminal, and a floating diffusion (FD) 16 receiving the charge transferred in a floating state to transmit it to a sense amp 17.
According to the operation of this linear CCD, when shift gate 11 or 12 is in the ON state, a signal that is photoelectrically-converted in a corresponding photodiode (PD) of the array 10 is transferred to one of the charge transfer parts 13 and 14. The photodiode array is divided into even numbers and odd numbers to transfer the signal to the charge transfer parts located above and below, respectively, in zigzags. For example, if the charge of the odd photodiodes is transferred to the upper part, that of the even photodiodes is transferred to the lower part.
Then, after transferring the signals accumulated in the charge well in the direction of the right side in FIG. 1 by the clock of the charge transfer parts 13 and 14, the signals are extracted by FD 16 and sense amp 17.
FIG. 2 shows in greater detail the portion AA of FIG. 1. FIG. 3A is a cross-sectional view taken along view-line III--III in FIG. 2. FIG. 3B shows the potential in this section.
A photodiode (photo cell) 20 forms a P-N junction with a channel stop region 26 and one side of a shift gate 21 as the boundary, in a P-type substrate 30. Shift electrodes (P1, P2) 23 of a charge transfer part, e.g., 13 or 14, are formed on the N-type doped substrate region with an insulating layer 31 imposed therebetween, respectively. Between shift electrodes 23 and photodiode 20, a shift gate 21 is formed on the substrate, with insulating layer 31 imposed therebetween. Channel stop region 26 is formed on the other side of shift gate 21. The part excluding photodiode 20 is covered with a light-shielding film 32 and an insulating layer 31' interposed therebetween.
Considering the operation of such conventional linear CCD, when a signal voltage is applied to shift gate (11 and 12 in FIG. 1 or 21 in FIG. 2 because only part of one side is shown), the potential 21' below shift gate 21 is lowered as shown in dotted line in FIG. 3B. Thus, charges 20' accumulated in the photodiode (shown in a slash mark for convenience sake of explanation) pass under the shift gate and transfer to a well region 23' formed below shift electrode 23. After once transferring the charge of the photodiode to the well 23', the applied voltage of the shift gate is made low immediately to thereby shield the path of the charge.
To shift charges to electrodes P1 and P2 of the charge transfer part, two values of "low" (of "0" V) and "high" (of a certain positive voltage of "H" V) are applied. That is, a pulsed clock repeating a high-low waveform is applied to transfer the charge to the output side.
In other words, for transferring the charge from the photodiode to the well below the shift electrode, in a state that no clock is applied to the shift gate (i.e., in an OFF state as compared to a switch), if applying the high (+V) voltage to the shift electrode and applying the high pulse to shift gate 21, the charge path under the shift gate is opened (is similarly to be turned on in case of switch). Thus, the charges accumulated in the photodiode are transferred to the potential well under the corresponding shift electrode of the charge transfer part that is in contact with the outlet side of the photodiode.
If the movement of the signal charge to the charge transfer part is done, the shift gate enters an OFF state to thereby isolate the photodiode and the channel of the charge transfer part. The clock of the charge transfer part is applied to the shift electrode, thereby transferring the signal charge in the direction of the OG and FD.
According to such a conventional linear CCD, since two shift gates should be utilized between the photodiode-array and the upper and lower charge transfer parts, the structure is complicated. In addition, it is attended with inconvenience that an external pin should be installed in the CCD package in order to apply the pulse to the shift gate.
Further, since the clock pulse of the charge transfer parts utilize the voltage between 0 to +H volt, the surface of the channel of the charge transfer part is not in the accumulation state. Thus, there is a problem that a leakage charge generated in the surface flows.
Since the shift gate 21 should be formed of polysilicon, in order to isolate it from the polysilicon of the charge transfer part, e.g., 13 or 14, the length of the region 30' of the substrate 30 where the photodiode communicates with the charge transfer part should be enlarged. Thus, when the shift gate enters the ON state, the distance that the signal charge should be passed is large, so that it takes a long time. Accordingly, the image lag phenomenon is liable to be caused. In order to prevent this phenomenon, the potential step of the photodiode and the charge transfer part should be enlarged.